ESD protection under grounded-up bond pads in 0.13 μm eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology

IEEE Electron Device Letters

Volumn 22, Issue 7, 2001, Pages 342-344

  Chou, Kuo Yu ^b,c   Chen, Ming Jer ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Copper metal; Die cracking; ESD; Fluorinated silicate glass; FSG; IMD; Intermetal dielectric; Low k; Stress mismatch; Wire bonding

Indexed keywords

DIE CRACKING; ELECTROSTATIC DISCHARGE PROTECTION; FLUORINATED SILICATE GLASS; GROUNDED UP BOND PAD; STRESS MISMATCH; WIRE BONDING;

BONDING; COMPUTER SIMULATION; COPPER; CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC MATERIALS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTROSTATICS; SILICATES; THERMAL STRESS;

CMOS INTEGRATED CIRCUITS;

EID: 0035397793     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.930685     Document Type: Article

References (4)

1. ESD protection under wire bonding pads
2. A manufacturable and reliable low-k inter-metal dielectric using fluorinated oxide (FSG)
3. Distributed ESD protection for high-speed integrated circuits
4. Addressing ESD for microprocessors and ASIC's in 21st century technologies