High throughput overlapped message passing for low density parity check codes

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 245-248

  Chen, Yanni ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

High throughput; Low density parity check codes; Overlapped message passing

Indexed keywords

OVERLAPPED MESSAGE PASSING;

ALGORITHMS; COMPUTER SIMULATION; DECODING; SCHEDULING;

BLOCK CODES;

EID: 0037699705     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1142/9789812796769_0039     Document Type: Conference Paper

References (5)

1. R. G. Gallager, "Low density parity check codes," IRE Trans. Info. Theory, vol. IT-8, pp. 21-28, 1962.
2. T. Zhang, and K.K. Parhi, "VLSI implementation oriented (3,k)-regular low-density parity-check codes," Proc. of 2001 IEEE Workshop on Signal Processing Systems, pp. 25-36, Sept. 2001.
3. D. J. C. MacKay, R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, pp. 1645, 1996.
4. D. Sridhara, T. Fuja, R. M. Tanner, "Low density parity check codes from permutation matrices," 2001 Conf. on Info. Sciences and Systems, The John Hopkins University, March 2001.
5. D. Hocevar, "LDPC code construction with flexible hardware implementation," to appear in Proc. of ICC'03, 2003.