High-k scaling of gate insulators: An insightful study

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3506, Issue , 1998, Pages 65-72

  Krishnan, Srinath ^a   Yeap, Geoffrey C F ^a,b   Yu, Bin ^a   Xiang, Qi ^a   Lin, Ming Ren ^a  

^a ADVANCED MICRO DEVICES   (United States)

^b MOTOROLA INC   (United States)

Author keywords

CMOS; Device scaling; FIBL; High k; MOSFETs; Off state current; Poly depletion; Tunneling

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INSULATORS; ELECTRON TUNNELING; HIGH TEMPERATURE PROPERTIES; MOSFET DEVICES; SEMICONDUCTOR DOPING; SILICA;

DEVICE SCALING; FRINGING-INDUCED BARRIER LOWERING; GATE INSULATOR; POLY DEPLETION; SOFTWARE PACKAGE MEDICO;

GATES (TRANSISTOR);

EID: 0037651359     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.323991     Document Type: Conference Paper

References (4)

1. National Technology Roadmap for Semiconductors (NTRS), Semiconductor Industry Association, 1997.
2. D. Buchnan and S-H Lo, "Reliability and Integration of Ultra-thin Gate Dielectrics for Advanced CMOS," Microelectronic Engineering, pp. 13-20, 1997.
3. W-K Shih, Investigation of Quantization Effects on Inversion Layer Carrier Transport in Deep Submicron Silicon MOSFETs, Ph.D. Thesis, The Univ. of Texas at Austin, Aug. 1997.
4. K. Chen et al., "Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects," IEEE T-ED, Vol. 44, pp. 1951-1957, Nov. 1997.