Cancellation technique to provide ESD protection for multi-GHz RF inputs

Electronics Letters

Volumn 39, Issue 3, 2003, Pages 284-286

  Hyvonen, S ^a   Joshi, S ^a   Rosenbaum, E ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTROSTATICS; INTEGRATED CIRCUIT MANUFACTURE;

ELECTROSTATIC DISCHARGES (ESD);

ELECTRIC DISCHARGES;

EID: 0037421742     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030221     Document Type: Article

References (8)

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2. MARLEY, J., TAN, D., and KRAZ, V.: 'Controlling ESD damage of ICs at various steps of back-end process'. EOS/ESD Symp. Proc., Portland, OR, USA, 2001, pp. 120-124
3. RICHIER, C., SALOME, P., MABBOUX, G., ZAZA, I., JUGE, A., and MORTINI, R: 'Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process'. EOS/ESD Symp. Proc., Anaheim, CA, USA, 2000, pp. 251-259
4. DABRAL, S., and MALONEY, T.J.: 'Basic ESD and I/O design' (Wiley, 1998)
5. LEROUX, P., and STEYAERT, M.: 'High-performance 5.2 GHz LNA with onchip inductor to provide ESD protection', Electron. Lett, 2001, 37, (7), pp. 467-469
6. JOSHI, S., and ROSENBAUM, E.: 'Compact modeling of vertical ESD protection NPN transistors for RF circuits'. EOS/ESD Symp. Proc., Charlotte, NC, USA, 2002, pp. 289-295
7. MALONEY, T.J., and KHURANA, N.: 'Transmission line pulsing techniques for circuit modeling'. EOS/ESD Symp. Proc., Minneapolis, MN, USA, 1985, pp. 49-54
8. BARTH, J., VERHAEGE, K., HENRY, L.G., and RICHNER, J.: 'TLP calibration, correlation, standards, and new techniques'. EOS/ESD Symp. Proc., Anaheim, CA, USA, 2000, pp. 85-96