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Volumn 146, Issue 3, 1999, Pages 124-129

Low-power circuit implementation for partial-product addition using pass-transistor logic

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BIPOLAR INTEGRATED CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC CURRENTS; LOGIC CIRCUITS;

EID: 0032658917     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19990328     Document Type: Article
Times cited : (19)

References (14)
  • 3
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    • Minimizing energy dissipation in high-speed multipliers'. Proceedings of IEEE international symposium on
    • FRIED, R.: 'Minimizing energy dissipation in high-speed multipliers'. Proceedings of IEEE international symposium on Low-power electronics and design, 1997, pp. 214-219
    • (1997) Low-power Electronics and Design , pp. 214-219
    • Fried, R.1
  • 4
    • 0029267856 scopus 로고
    • A 4.4 ns CMOS 54 × 54-b multiplier using pass-transistor multiplexer', IEEE
    • OHKUBO, N., SUZUKI, M., SHINBO, T., YAMANAKA, T., SHIMIZU, A., SASAKI, K., and NAKAGOME, Y.: 'A 4.4 ns CMOS 54 × 54-b multiplier using pass-transistor multiplexer', IEEE J. Solid-Stale Circuits, 1995, 30, (3), pp. 251-256
    • (1995) J. Solid-Stale Circuits , vol.30 , Issue.3 , pp. 251-256
    • Ohkubo, N.1    Suzuki, M.2    Shinbo, T.3    Yamanaka, T.4    Shimizu, A.5    Nakagome, Y.6
  • 5
    • 0025419522 scopus 로고
    • A 3.8 ns 16 × 16-b multiplier using complementery pass-transistor loaic'
    • YANO, K., YAMANAKA, T., NISHIDA, T., SAITO, M., SHIMOHIGASHI, K., and SHIMIZU, A.: 'A 3.8 ns 16 × 16-b multiplier using complementery pass-transistor loaic', IEEE J. Solid Stale Circuits, 1990, 25, (4), pp. 388-395
    • (1990) IEEE J. Solid Stale Circuits , vol.25 , Issue.4 , pp. 388-395
    • Yano, K.1    Yamanaka, T.2    Nishida, T.3    Saito, M.4    Shimizu, A.5
  • 7
    • 0024681856 scopus 로고
    • Realization of transmission-gate conditional-sum (TGCS) adders with low latency time'
    • ROTHERMEL, A., HOSTICKA, BJ., TROSTER, G., and ARNDT, J.: 'Realization of transmission-gate conditional-sum (TGCS) adders with low latency time', IEEE J. Solid-State Circuits, 1989, 24, (6), pp. 558-561
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.6 , pp. 558-561
    • Rothermel, A.1    Hosticka, B.J.2    Arndt, J.3
  • 10
    • 0028405787 scopus 로고
    • 4-2 compressor with complementary pass-transistor lode'
    • KANIE, Y., KUBOTA, Y., TOYOYAMA, S., IWASE, Y., and TSUCHIMOTO, S.: '4-2 compressor with complementary pass-transistor lode', IEICE Trails. Electron., 1994, E77-C, (4), pp. 647-649
    • (1994) IEICE Trails. Electron. , vol.77 , Issue.4 , pp. 647-649
    • Kanie, Y.1    Kubota, Y.2    Toyoyama, S.3    Tsuchimoto, S.4
  • 11
    • 0032545853 scopus 로고    scopus 로고
    • Design of high-speed low-power 3-2 counter and
    • HSIAO, S.F., JIANG, M.R., and YEH, J.S.: 'Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers', Electron. Lett., 1998, 34, (4), pp. 341-343
    • (1998) Electron. Lett. , vol.34 , Issue.4 , pp. 341-343
    • Hsiao, S.F.1    Yeh, J.S.2
  • 13
    • 33749754056 scopus 로고
    • A highspeed, low-power, swing restored pass-transistor logic based multiply and
    • PARAMESWAR, A., HARA, H., and SAKURAI, T.: 'A highspeed, low-power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications'. Proceedings of IEEE conference on Custom integrated circuits, 1994, pp. 27S-28T
    • (1994) Custom Integrated Circuits
    • Parameswar, A.1    Sakurai, T.2    On, A.3
  • 14
    • 0026925486 scopus 로고
    • A 54 x 54-b regularly structured tree multiplier'
    • GOTO, G., SATO, T., NAKAJIMA, M., and SUKEMURA, T.: 'A 54 x 54-b regularly structured tree multiplier', IEEE J. Solid-State Circuits, 1992, 27, (9) pp. 1229-1236
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.9 , pp. 1229-1236
    • Goto, G.1    Sato, T.2    Sukemura, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.