Timing driven floorplanning on programmable hierarchical targets

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1998, Pages 85-92

  Senouci, S A ^a   Amoura, A ^a   Krupnova, H ^a   Saucier, G ^a  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

FLOORPLANNING; PROGRAMMABLE HIERARCHICAL TARGETS;

TIMING CIRCUITS;

EID: 0031634256     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/275107.275123     Document Type: Conference Paper

References (12)