A detailed analysis of power-supply noise attenuation in bandgap voltage references

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 2, 2003, Pages 185-197

  Giustolisi, Gianluca ^a   Palumbo, Gaetano ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

Bandgap voltage reference; Circuit analysis; CMOS analog integrated circuits; Frequency domain analysis; Power supply noise attenuation

Indexed keywords

ATTENUATION; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; FREQUENCY DOMAIN ANALYSIS; LINEAR INTEGRATED CIRCUITS; POWER SUPPLY CIRCUITS; SPURIOUS SIGNAL NOISE; VOLTAGE MEASUREMENT;

BANDGAP VOLTAGE REFERENCE; POWER SUPPLY NOISE ATTENUATION;

ELECTRIC NETWORK ANALYSIS;

EID: 0037303673     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.808188     Document Type: Article

References (38)

1. P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, III ed. New York: Wiley, 1993.
2. J. Millman and A. Grabel, Microelectronics, II ed. New York: McGraw-Hill, 1987.
3. K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems. New York: McGraw Hill, 1994.
4. D. A. Johns and K. Martin, Analog Integrated Circuit Design,. New York: Wiley, 1997.
5. R. van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters. Norwell, MA: Kluwer, 1994.
6. R. J. Widlar, "New developments in IC voltage regulators," IEEE J. Solid-State Circuits, vol. SC-6, pp. 2-7, Feb. 1971.
7. K. E. Kuijk, "A precision reference voltage source," IEEE J. Solid-State Circuits, vol. SC-8, pp. 222-226, June 1973.
8. A. P. Brokaw, "A simple three-terminal IC bandgap reference," IEEE J. Solid-State Circuits, vol. SC-9, pp. 388-393, Dec. 1974.
9. G. C. M. Meijer, P. C. Schmale, and K. van Zalinge, "A new curvature-corrected bandgap reference," IEEE J. Solid-State Circuits, vol. SC-17, pp. 1139-1143, Dec. 1982.
10. B. Song and P. R. Gray, "A precision curvature-compensated CMOS bandgap reference," IEEE J. Solid-State Circuits, vol. SC-18, pp. 634-643, Dec. 1983.
11. C. Y. Wu and S. Y. Chin, "High-precision curvature-compensated CMOS band-gap voltage and current references," Analog Integ. Circuits Signal Process., vol. 2, pp. 207-215, 1992.
12. I. Lee, G. Kim, and W. Kim, "Exponential curvature-compensated BiCMOS bandgap references," IEEE J. Solid-State Circuits, vol. 29, pp. 1396-1403, Nov. 1994.
13. T. C. Banwell, "Error amplifier limitations in low voltage regulators using only NPN transistors," IEEE Trans. Circuits Syst. II, vol. 42, pp. 220-224, Mar. 1995.
14. G. A. Rincon-Mora and P.E. Allen, "A 1.1-V current-mode and piece-wise-linear curvature-corrected bandgap reference," IEEE J. Solid-State Circuits, vol. 33, pp. 1551-1554, Oct. 1998.
15. M. Gunawan, G. C. M. Meijer, J. Fonderie, and J. H. Huijsing, "A curvature-corrected low-voltage bandgap reference," IEEE J. Solid-State Circuits, vol. 28, pp. 667-670, June 1993.
16. R. J. Reay, E. H. Klaassen, and G. T. A. Kovacs, "A micromachined low-power temperature-regulated bandgap voltage reference," IEEE J. Solid-State Circuits, vol. 30, pp. 1374-1381, Dec. 1995.
17. A. van Staveren, J. van Velzen, C. J. M. Verhoeven, and A. H. M. van Roermund, "An integrable second-order compensated bandgap reference for 1V supply," Analog Integ. Circuits Signal Process., vol. 8, pp. 69-81, 1995.
18. P. Malcovati, F. Maloberti, C. Fiochi, and M. Pruzzi, "Curvature-compensated BiCMOS bandgap with 1-V supply voltage," IEEE J. Solid-State Circuits, vol. 36, pp. 1076-1081, July 2001.
19. Y. P. Tsividis and R. W. Ulmer, "A CMOS voltage reference," IEEE J. Solid-State Circuits, vol. SC-13, pp. 774-778, Dec. 1978.
20. E. A. Vittoz and O. Neyroud, "A low-voltage CMOS bandgap reference," IEEE J. Solid-State Circuits, vol. SC-14, pp. 573-577, June 1979.
21. G. Tzanateas, C. A. T. Salama and Y. P. Tsividis, "A CMOS bandgap voltage reference," IEEE J. Solid-State Circuits, vol. SC-14, pp. 655-657, June 1979.
22. K. M. Tham and K. Nagaraj, "A low supply voltage high PSRR voltage reference in CMOS process," IEEE J. Solid-State Circuits, vol. 30, pp. 586-590, May 1995.
23. T. Kawahara, S. I. Saeki, Y. Jyouno, N. Miyamoto, T. Kobayashi, and K. Kimura, "Internal voltage generator for low voltage quarter-micrometer flash memories," IEEE J. Solid-State Circuits, vol. 33, pp. 126-132, Jan. 1998.
24. Y. Jiang and E. K. F. Lee, "Design of low-voltage bandgap reference using transimpedance amplifier," IEEE Trans. Circuits Syst. II, vol. 47, pp. 552-555, June 2000.
25. A. van Staveren, A. J. M. Verhoeven, and A. H. M. van Roermund, "The design of low-noise bandgap references," IEEE J. Solid-State Circuits, vol. 43, pp. 290-300, Apr. 1996.
26. M. Ferro, F. Salerno, and R. Castello, "A floating CMOS bandgap voltage reference for differential applications," IEEE J. Solid-State Circuits, vol. 24, pp. 690-697, June 1989.
27. G. Niccolini and D. Senderowicz, "A CMOS bandgap reference for differential signal processing," IEEE J. Solid-State Circuits, vol. 26, pp. 41-50, Jan. 1991.
28. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1999.
29. B. Rasavi, RF Microelectronics. Englewood, Cliffs, MA: Prentice-Hall, 1998.
30. W. J. Dally and J. W. Paulton, Digital Systems Engineering. Cambridge, MA: Cambridge Univ. Press, 1999
31. S. H. Hall, G. Hall, and J. A. McCall, High-Speed Digital System Design (A Handbook of Interconnect Theory and Design Practice). Singapore: Wiley Interscience, 2000.
32. G. Giustolisi, G. Palumbo, and S. Pennisi, "Power supply rejection of widlar bandgap voltage reference," in Proc. MIXDES 2000, Gdynia, Poland, Jun. 2000, pp. 271-274.
33. G. Giustolisi and G. Palumbo, "Detailed frequency analysis of power supply rejection in Brokaw bandgap," in Proc. IEEE ISCAS 2001, Vol. I, Sydney, Australia, May 2001, pp. 731-734.
34. H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-State Circuits, vol. 34, pp. 670-674, May 1999.
35. A. J. Annema, "Low-power bandgap references featuring DTMOSTSs," IEEE J. Solid-State Circuits, vol. 34, pp. 949-955, July 1999.
36. H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, H. Hidaka, T. Tachibana, and K. Kimura, "A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme," IEEE J. Solid-State Circuits, vol. 34, pp. 1084-1090, Aug. 1999.
37. M. S. J. Steyaert and W. M. C. Sansen, "Power supply rejection ratio in operational transconductance amplifiers," IEEE Trans. Circuits Syst., vol. 37, pp. 1077-1084, Sept. 1990.
38. E. Säckinger, J. Goette, and W. Guggenbühl, "A general relationship between amplifier parameters, and its application to PSRR improvement," IEEE Trans. Circuits Syst., vol. 38, pp. 1173-1181, Oct. 1991.