Two-dimensional DCT/IDCT architecture

IEE Proceedings: Computers and Digital Techniques

Volumn 150, Issue 1, 2003, Pages 2-10

  Aggoun, A ^a   Jalloh, I ^a  

^a DE MONTFORT UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COSINE TRANSFORMS; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE; VLSI CIRCUITS;

RESIDUE NUMBER SYSTEM (RNS);

COMPUTER ARCHITECTURE;

EID: 0037282155     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20030063     Document Type: Conference Paper

References (13)

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3. WALLACE, G.K.: 'The JPEG still picture compression standard', Commun. ACM, 1991, 34, (4), pp. 30-40
4. LEGALL, D.: 'A video compression standard for multimedia applications', Commun. ACM, 1991, 34, (4), pp. 46-58
5. ISO/IEC DIS 13818 - 2, MPEG-2 Video, Draft Int. Standard
6. HSIA, S.C., LIU, B.D., YANG, J.F., and BAI, B.L.: 'VLSI implementation of parallel coefficient-by-coefficient two-dimentional IDCT processor', IEEE Trans. Circuits Syst. Video Technol., 1995, 5, (5), pp. 396-406
7. CHIANG, J.S., CHUI, Y.F., and CHANG, T.H.: 'A high throughput 2-dimensional DCT/IDCT architecture for real-time and video system'. Proceedings of IEEE Int. Conf. on Electronic circuits and systems, Malta, Sept. 2001, 2, pp. 867-870
8. FERNANDEZ, P.G., GARCIA, A., RAMIREZ, J., and LLORIS, A.: Fast RNS-based 2D-DCT computation on field-programmable devices'. Proceedings of IEEE Workshop on Signal processing systems, Louisiana, USA, Oct. 2000, pp. 365-373
9. CHANG, Y.T., and WANG, C.L.: 'New systolic array implementation of the 2D discrete cosine transform', IEEE Trans. Circuits Syst. Video Technol., 1995, 5, (2), pp. 150-157
10. AGGOUN, A., IBRAHIM, M.K., and ASHUR, A.: Bit-level pipelined digit-serial array processors', IEEE Trans. Circuit Syst., 1998, 45, (7), pp. 857-868
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12. AGGOUN, A.: 'Two's complement parallel multiplier', Electron. Lett., 1998, 34, (16), pp. 1570-1571
13. WEY, C.L., and CHANG, T.Y.: 'Design and analysis of VLSI based parallel multipliers', IEE Proc., Comput. Digit. Tech., 1990, 137, (4), pp. 328-336