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Electronics Letters
Volumn 34, Issue 16, 1998, Pages 1570-1571
Two's complement parallel multiplier
Author keywords

[No Author keywords available]
Indexed keywords

COMPUTER ARCHITECTURE; PARALLEL PROCESSING SYSTEMS;
EID: 0032490785     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981142     Document Type: Article
Times cited : (2)
References (4)
  • 1
    • 0025465214 scopus 로고
    • Design and analysis of VLSI-based parallel multipliers
    • WEY, C.L., and CHANG, T.Y.: 'Design and analysis of VLSI-based parallel multipliers', IEE Proc. E, 1990, 137, (4), pp. 328-336
    • (1990) IEE Proc. E , vol.137 , Issue.4 , pp. 328-336
    • Wey, C.L.1    Chang, T.Y.2
  • 2
    • 0026908021 scopus 로고
    • New parallel multiplier design
    • MEKHALLALATI, M.C., and IBRAHIM, M.K.: 'New parallel multiplier design', Electron. Lett., 1992, 28, (17), pp. 1650-1651
    • (1992) Electron. Lett. , vol.28 , Issue.17 , pp. 1650-1651
    • Mekhallalati, M.C.1    Ibrahim, M.K.2
  • 3
    • 0015724965 scopus 로고
    • A two's complement parallel array multiplication algorithm
    • BAUGH, C.R., and WOOLEY, B.A.: 'A two's complement parallel array multiplication algorithm', IEEE Trans. Comput., 1973, 33, pp. 1045-1047
    • (1973) IEEE Trans. Comput. , vol.33 , pp. 1045-1047
    • Baugh, C.R.1    Wooley, B.A.2
  • 4
    • 0021510065 scopus 로고
    • Optimised bit level systolic array for convolution
    • McCANNY, MCWHIRTER, J.G. and WOOD, K.: 'Optimised bit level systolic array for convolution', IEE Proc. F. 1984, 131, (6), pp. 632-637
    • (1984) IEE Proc. F. , vol.131 , Issue.6 , pp. 632-637
    • McCanny1    Mcwhirter, J.G.2    Wood, K.3

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.