Bus architecture for low-power VLSI digital circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 21-24

  Cardarilli, Gian Carlo ^a   Salmeri, Marcello ^a   Salsano, Adelio ^a   Simonelli, Osvaldo ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; ENERGY UTILIZATION; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; SIGNAL PROCESSING; SIGNAL RECEIVERS; VLSI CIRCUITS;

BUS ARCHITECTURE; CHARGED CONTROLLED DRIVER; INTERCONNECTION BUSSES; LOGIC INVERTER; POWER CONSUMPTION; POWER REDUCTION; VOLTAGE SWING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029694610     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)