Dual-mode pipeline A/D converter for direct conversion receivers

Electronics Letters

Volumn 38, Issue 19, 2002, Pages 1101-1103

  Sumanen, Lauri ^a   Halonen, K ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CODE DIVISION MULTIPLE ACCESS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; OPERATIONAL AMPLIFIERS; SIGNAL RECEIVERS;

POWER DISSIPATION;

ANALOG TO DIGITAL CONVERSION;

EID: 0037068698     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020826     Document Type: Article

References (3)

1. GINETTI, B., and JESPERS, P.: 'A 1.5 Ms/s 8-bit Pipelined RSD A/D Converter'. European Solid-State Circuits Conference (ESSCIRC) Digest of Technical Papers, Sep. 1990, pp. 137-140.
2. SUMANEN, L., WALTARI, M., and HALONEN, K.: 'Optimizing the Number of Parallel Channels and the Stage Resolution in Time Interleaved Pipeline A/D Converters'. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'00), May 2000, pp. V-613-616.
3. NAGARAJ, K., FETTERMAN, H.S., ANIDJAR, J., LEWIS, S.H., and RENNINGER, R.G.: 'A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers', IEEE Journal of Solid-State Circuits, Mar. 1997, 32, (3), pp. 312-320.