2-1 Addition and related arithmetic operations with threshold logic

IEEE Transactions on Computers

Volumn 45, Issue 9, 1996, Pages 1062-1067

  Vassiliadis, Stamatis ^a   Cotofana, Sorin ^a   Bertels, Koen ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b UNIVERSITY OF NAMUR   (Belgium)

Author keywords

Binary adders; Binary comparison; Computer arithmetic; Majority circuits; Neural networks; Threshold logic

Indexed keywords

ADDERS; BOOLEAN FUNCTIONS; FEEDFORWARD NEURAL NETWORKS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; POLYNOMIALS; THRESHOLD LOGIC;

BINARY ADDITION; BINARY COMPARISON; COMPUTER ARITHMETIC; FEED FORWARD LINEAR THRESHOLD GATES; MAJORITY CIRCUITS;

DIGITAL ARITHMETIC;

EID: 0030244775     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.537130     Document Type: Article

References (11)

1. S. Muroga, "The Principle of Majority Decision Elements and the Complexity of their Circuits," Proc. Int'l Conf. Information Processing, pp. 400-407, UNESCO House, Paris, June 1959.
2. R. Minnick, "Linear-Input Logic," IRE Trans. Electronic Computers, vol. 10, pp. 6-16, Mar. 1961.
3. S. Muroga, "Threshold Logic and its Applications," John Wiley and Sons, 1971.
4. K. Siu, V. Roychowdhury, and T. Kailath, "Depth-Size Tradeoffs for Neural Computation," IEEE Trans. Computers, vol. 40, no. 12, pp. 1,402-1,412, Dec. 1991.
5. N. Alon and J. Bruck, "Explicit Construction of Depth-2 Majority Circuits for Comparison and Addition," Technical Report RJ 8300 (75661), IBM Research Division, Aug. 1991.
6. S. Cotofana and S. Vassiliadis, "Periodic Symmetric Functions with Feed-Forward Neural Networks," NEURAP '95/'96 Neural Networks and their Applications, pp. 215-221, Marseille, Mar. 1996.
7. T. Shibata and T. Ohmi, "A Functional MOS Transistor Featuring Gate-Level = Weighted Sum and Threshold Operations," IEEE Trans. Electron Devices, vol. 39, pp. 1,444-1,455, June 1992.
8. T. Shibata and T. Ohmi, "Neuron MOS Binary-Logic Integrated Circuits - Part I: Design Fundamantals for Soft-Hardware Circuit Implementation," IEEE Trans. Electron Devices, vol. 40, pp. 570-575, Mar. 1993.
9. T. Shibata and T. Ohmi, "Neuron MOS Binary-Logic Integrated Circuits - Part II: Simplifying Techniques of Circuit Configration and their Practical Applications," IEEE Trans. Electron Devices, vol. 40, pp. 974-979, May 1993.
10. K. Siu and J. Bruck, "On the Power of Threshold Circuits with Small Weights," SIAM J. Discrete Math., pp. 423-435, Aug. 1991.
11. V. Roychowdhury, A. Orlitsky, and K. Y. Siu, "Lower Bounds on Threshold and Related Circuits via Communication Complexity," IEEE Trans. Information Theory, vol. 40, no. 2, pp. 467-474, Mar. 1994.