Power consumption behaviour of multiplier block algorithms

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Demirsoy, Süleyman Sirri ^a   Dempster, Andrew G ^a   Kale, Izzet ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRIC POWER UTILIZATION; GRAPH THEORY;

MULTIPLIER BLOCKS (MB);

DIGITAL FILTERS;

EID: 0036973841     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Bull D. R. and D H Horrocks, "Primitive operator digital filters", IEE Proceedings G, vol 138, no 3, pp401-412, Jun 1991
2. A G Dempster and M D Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters" IEEE Trans Circuits and Systems II, vol 42, no 9, pp569-577, September 1995
3. Dempster A. G., S. S. Demirsoy, I. Kale, "Designing Multiplier Blocks with Low Logic Depth", IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), vol. 5, pp. 773-776, Arizona, US, May 2002
4. Demirsoy S. S., A. G. Dempster and I. Kale, "Power Analysis of Multiplier Blocks", IEEE Int. Symp. on Circuits and Systems (ISCAS'2002), vol.1, pp.297-300, Arizona, US, May 2002
5. Chandrakasan A.P. and R.W. Brodersen, "Minimising power consumption in digital CMOS circuits", Proc. IEEE, vol. 83, pp. 498-523, April 1995.
6. http://www.cmsa.wmin.ac.uk/̃demirss/gpscore