Power analysis of multiplier blocks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Demirsoy, Süleyman Sirri ^a   Dempster, Andrew G ^a   Kale, Izzet ^a  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS; MULTIPLYING CIRCUITS; OPTIMIZATION;

GLITCH-PATH METHOD; MULTIPLIER BLOCKS; REDUCED ADDER GRAPH ALGORITHM; XILINX VIRTEX DEVICE;

FIR FILTERS;

EID: 0036296550     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Primitive operator digital filters
2. Constant integer multiplication using minimum adders
3. Use of minimum-adder multiplier-blocks in FIR digital filters
4. Reduced complexity primitive operator FIR filters for low power dissipation
5. Designing multiplier blocks with low logic depth
6. Minimising power consumption in digital CMOS circuits
7. Transition analysis in multiplier-block based FIR filter structures