A design space exploration framework for reduced bit-width instruction set architecture (rISA) design

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2002, Pages 120-125

  Halambi, Ashok ^a   Shrivastava, Aviral ^a   Biswas, Partha ^a   Dutt, Nikil ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Compressed instruction set; Design space exploration; Dual instruction set; Reduced bit width instruction set; Register pressure; rISA; Thumb

Indexed keywords

CODES (SYMBOLS); COMPUTER SIMULATION; EMBEDDED SYSTEMS; PROGRAM PROCESSORS; ROM;

PROCESSOR ARCHITECTURES; SPACE EXPLORATION FRAMEWORK;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0036956947     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581227.581228     Document Type: Conference Paper

References (15)

1. ARCtangent-A5 microprocessor Technical Manual. ARC Cores, http://www.arccores.com.
2. ARM7TDMI Technical Manual ARM, http://www.arm.com.
3. Cisco 12000 Series Router Specifications Manual. CISCO, http://www.cisco.com.
4. Compaq iPAQ PocketPC Specifications Maual. COMPAQ, http://www.compaq.com.
5. Nokia 9210 Specifications. NOKIA, http://www.nokia.nl.
6. ST100 Technical Manual. STMicroelectronics, http://www.st.com.
7. P. Briggs, K. Cooper, and L. Torczon. Improvements to graph coloring register allocation. In Proceedings of SIGPLAN Conference on Programming Language Design and Implementation, 1994.
8. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In Proc. of Design Automation and Test in Europe, 1999.
9. A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau. An efficient compiler technique for code size reduction using reduced bit-width isas. In Proc. of Design Automation and Test in Europe, 2002.
10. A. Halambi, A. Shrivastava, N. Dutt, and A. Nicolau. A customizable compiler framework for embedded systems. In SCOPES, 2001.
11. A. Khare, N. Savoiu, A. Halambi, P. Grun, N. Dutt, and A. Nicolau. V-SAT: A visual specification and analysis for system-on-chip exploration. In Proceedings of EUROMICRO-99, 1999.
12. K. Kissell. MIPS16: High-density MIPS for the embedded market. Silicon Graphics MIPS Group, 1997.
13. A. Nicolau and S. Novack. Trailblazing: A hierarchical approach to percolation scheduling. Proc. of Intn'l Conf. on Parallel Processing, 1993.
14. S. Novack and A. Nicolau. Resource directed loop pipelining: Exposing just enough parallelism. The Computer Journal, 1997.
15. X. M. Young-Jun Kwon and H. J. Lee. PARE: instruction set architecture for efficient code size reduction. Electronics Letters, 35(24):2098-2099, November 1999.