PARE: Instruction set architecture for efficient code size reduction

Electronics Letters

Volumn 35, Issue 24, 1999, Pages 2098-2099

  Kwon, Young Jun ^a   Ma, Xiarong ^b   Lee, Hyuk Jae ^b  

^a MIPS Technologies Inc   (United States)

^b LOUISIANA TECH UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); DATA COMPRESSION; GRAPH THEORY;

PARTITIONED REGISTERS EXTENSION (PARE);

REDUCED INSTRUCTION SET COMPUTING;

EID: 0033221305     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19991420     Document Type: Article

References (5)

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2. SWEETMAN, D.: 'See MIPS run' (Morgan Kaufmann, San Francisco, CA, USA, 1999)
3. ARAUJO, G., and MALIK, S.: 'Optimal code generation for embedded memory nonhomogeneous register architectures'. Proc. Int. Symp. on Systems Synthesis, 1995, pp. 36-41
4. BERSON, D., GUPTA, R., and SOFFA, M.: 'URSA: A unified resource allocator for registers and functional units in VLIW architecture'. Technical Report 92-21, University of Pittsburgh, Pittsburgh, PA, USA, 1992
5. ZHANG, Y., and LEE, H.: 'Register allocation over a dependence graph'. Proc. Int. Workshop on Compiler and Architecture Support for Embedded Systems, 1999, pp. 171-176