Evaluation of circuit approaches in Partially Depleted SOI-CMOS

IEEE International SOI Conference

Volumn , Issue , 2000, Pages 98-99

  Das, Koushik K ^a   Brown, Richard B ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; BUFFER CIRCUITS; CAPACITANCE; COMPUTER SIMULATION; DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR); LOGIC DESIGN; SILICON ON INSULATOR TECHNOLOGY;

DYNAMIC LOGIC DELAYS;

CMOS INTEGRATED CIRCUITS;

EID: 0034473804     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)