-
3
-
-
0028483922
-
The uniform memory hierarchy model of computation
-
B. Alpern, L. Carter, E. Feig and T. Selker. The Uniform Memory Hierarchy Model of Computation. In Algorithmica, vol. 12, (1994), 72-129.
-
(1994)
Algorithmica
, vol.12
, pp. 72-129
-
-
Alpern, B.1
Carter, L.2
Feig, E.3
Selker, T.4
-
4
-
-
0025028257
-
The tera computer system
-
June 1990
-
R. Alverson, D. Callahan, D Cummings, B. Koblenz, A. Porterfield, B. Smith. The Tera Computer System. ACM International Conference on Supercomputing, pp. 1-6, June 1990.
-
(1990)
ACM International Conference on Supercomputing
, pp. 1-6
-
-
Alverson, R.1
Callahan, D.2
Cummings, D.3
Koblenz, B.4
Porterfield, A.5
Smith, B.6
-
5
-
-
0033880614
-
Predicting performance on SMP's. A case study: The SGI power challenge
-
May
-
N.M. Amato, J. Perdue, A. Pietracaprina, G. Pucci, and M. Mathis. Predicting performance on SMP's. A case study: The SGI Power Challenge. In Proc. International Parallel and Distributed Processing Symposium, IPDPS 2000, Cancun, MEX, pages 729-737, May 2000.
-
(2000)
Proc. International Parallel and Distributed Processing Symposium, IPDPS 2000, Cancun, MEX
, pp. 729-737
-
-
Amato, N.M.1
Perdue, J.2
Pietracaprina, A.3
Pucci, G.4
Mathis, M.5
-
8
-
-
0012523249
-
SPORT: A scalable computer with a pipelined memory hierarchy
-
Manuscript, November
-
G. Bilardi, K. Ekanadham, P. Pattnaik. SPORT: A Scalable Computer with a Pipelined Memory Hierarchy. Manuscript, November 2001.
-
(2001)
-
-
Bilardi, G.1
Ekanadham, K.2
Pattnaik, P.3
-
10
-
-
0031260815
-
Processor-time tradeoffs under bounded-speed message propagation. Part I: Upper bounds
-
G. Bilardi and F.Preparata Processor-time tradeoffs under bounded-speed message propagation. Part I: upper bounds. Theory of Computing Systems, Vol. 30, 523-546, 1997.
-
(1997)
Theory of Computing Systems
, vol.30
, pp. 523-546
-
-
Bilardi, G.1
Preparata, F.2
-
11
-
-
0040115155
-
Processor-time tradeoffs under bounded-speed message propagation. Part II: Lower bounds
-
G. Bilardi and F.Preparata Processor-time tradeoffs under bounded-speed message propagation. Part II: lower bounds. Theory of Computing Systems, Vol. 32, 531-559, 1999.
-
(1999)
Theory of Computing Systems
, vol.32
, pp. 531-559
-
-
Bilardi, G.1
Preparata, F.2
-
12
-
-
84951156707
-
An approach toward an analytical characterization of locality and its portability
-
A. Veidenbaum and H. Joe Eds., IEEE Computer Press
-
G. Bilardi and E. Peserico An Approach toward an Analytical Characterization of Locality and its Portability. Proceedings of International Workshop on Innovative Architectures (IWIA01), A. Veidenbaum and H. Joe Eds., IEEE Computer Press, (2001).
-
(2001)
Proceedings of International Workshop on Innovative Architectures (IWIA01)
-
-
Bilardi, G.1
Peserico, E.2
-
13
-
-
0003575828
-
A characterization of temporal locality and its portability across memory hierarchies
-
G. Bilardi and E. Peserico A Characterization of Temporal Locality and its Portability Across Memory Hierarchies. ICALP 2001, International Colloquium on Automata, Languages, and Programming, Crete, July 2001.
-
ICALP 2001, International Colloquium on Automata, Languages, and Programming, Crete, July 2001
-
-
Bilardi, G.1
Peserico, E.2
-
14
-
-
84958752903
-
On the space and access complexity of computation dags
-
G. Bilardi, A. Pietracaprina, and P. D'Alberto. On the space and access complexity of computation dags. 26th Workshop on Graph-Theoretic Concepts in Computer Science, Konstanz, Germany, June 2000.
-
26th Workshop on Graph-Theoretic Concepts in Computer Science, Konstanz, Germany, June 2000
-
-
Bilardi, G.1
Pietracaprina, A.2
D'Alberto, P.3
-
15
-
-
0022093446
-
A model of computation for VLSI with related complexity results
-
July
-
B. Chazelle and L. Monier. A Model of Computation for VLSI with Related Complexity Results. Journal of the ACM, 32(3):573-588, July 1985.
-
(1985)
Journal of the ACM
, vol.32
, Issue.3
, pp. 573-588
-
-
Chazelle, B.1
Monier, L.2
-
17
-
-
0000078545
-
Dynamic storage allocation in the ATLAS computer, including an automatic use of a backing store
-
J. Fotheringham. Dynamic storage allocation in the ATLAS computer, including an automatic use of a backing store. Communication of the ACM, 4, 10, pp. 435-436, (1961).
-
(1961)
Communication of the ACM
, vol.4
, Issue.10
, pp. 435-436
-
-
Fotheringham, J.1
-
19
-
-
0000256277
-
On the physical design of PRAMs
-
December
-
F. Abolhassan, R. Drefenstedt, J. Keller, W.J. Paul, and D. Scheerer. On the Physical Design of PRAMs. Computer Journal, 36(8), pp. 756-762, December 1993.
-
(1993)
Computer Journal
, vol.36
, Issue.8
, pp. 756-762
-
-
Abolhassan, F.1
Drefenstedt, R.2
Keller, J.3
Paul, W.J.4
Scheerer, D.5
-
20
-
-
84867955438
-
The ultrascalar processor: An asymptotically scalable superscalar microarchitecture
-
IEEE Computer Society
-
D.S. Henry, B.C. Kuszmaul. and V. Viswanath The Ultrascalar Processor: An Asymptotically Scalable Superscalar Microarchitecture. Proceedings ARVLSI'99, Atlanta GA, March 21-24, pp. 256-273, IEEE Computer Society, 1999.
-
(1999)
Proceedings ARVLSI'99, Atlanta GA, March 21-24
, pp. 256-273
-
-
Henry, D.S.1
Kuszmaul, B.C.2
Viswanath, V.3
-
21
-
-
0003831797
-
Area-efficient VLSI computation
-
Ph.D. Thesis, Department of Computer Science, Carnegie Mellon University, October
-
C. Leiserson Area-Efficient VLSI Computation. Ph.D. Thesis, Department of Computer Science, Carnegie Mellon University, October 1981.
-
(1981)
-
-
Leiserson, C.1
-
22
-
-
0000771570
-
A model of sequential computation with pipelined access to memory
-
F. Luccio and L. Pagli. A model of sequential computation with pipelined access to memory. Mathematical Systems Theory, 26(4), 343-356, 1993.
-
(1993)
Mathematical Systems Theory
, vol.26
, Issue.4
, pp. 343-356
-
-
Luccio, F.1
Pagli, L.2
-
23
-
-
0012526136
-
Data prefetching: A cost/performance analysis
-
MIT, October
-
C. Metcalf. Data prefetching: a cost/performance analysis. Area Exam, MIT, October 1993.
-
(1993)
Area Exam
-
-
Metcalf, C.1
-
24
-
-
0014701246
-
Evaluation techniques for storage hierarchies
-
R.L. Mattson, J. Gecsei, D.R. Slutz, and I.L. Traiger. Evaluation Techniques for Storage Hierarchies. IBM System Journal, No. 2, 78-117, 1970.
-
(1970)
IBM System Journal
, vol.2
, pp. 78-117
-
-
Mattson, R.L.1
Gecsei, J.2
Slutz, D.R.3
Traiger, I.L.4
-
25
-
-
0012524440
-
Special issue on cache memory and related problems
-
V. Milutinovic and M. Valero (Guest Eds.); February
-
V. Milutinovic and M. Valero (Guest Eds.) Special Issue on Cache Memory and Related Problems. IEEE Transactions on Computers, February 1999.
-
(1999)
IEEE Transactions on Computers
-
-
-
27
-
-
0020289466
-
Architecture and applications of the HEP multiprocessor system
-
Smithv, B. J.: Architecture and applications of the HEP multiprocessor system, Signal Processing IV, 298 (1981), 241-248.
-
(1981)
Signal Processing IV
, vol.298
, pp. 241-248
-
-
Smithv, B.J.1
-
29
-
-
0002655387
-
General purpose parallel architectures
-
(J.v. Leeuwen, ed.), Elsevier-MIT Press
-
Valiant, L.G.: General purpose parallel architectures, Handbook for Theor. Computer Science (J.v. Leeuwen, ed.), Elsevier-MIT Press, 1990.
-
(1990)
Handbook for Theor. Computer Science
-
-
Valiant, L.G.1
-
30
-
-
84896772765
-
External memory algorithms
-
(G.Bilardi et al. Eds.), Springer Verlag, Venic, August
-
J.S Vitter. External Memory Algorithms. Invited paper in Proc. 6th Annual European Symposium on Algorithms. (G.Bilardi et al. Eds.), Springer Verlag, Venic, August 1998, 1-25.
-
(1998)
Proc. 6th Annual European Symposium on Algorithms
, pp. 1-25
-
-
Vitter, J.S.1
|