Pipelined memory hierarchies: Scalable organizations and application performance

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2001-January, Issue , 2000, Pages 45-52

  Bilardi, G ^a   Ekanadham, K ^b   Pattnaik, P ^b  

^a UNIVERSITY OF PADOVA   (Italy)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Memory management

Indexed keywords

COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; SOCIETIES AND INSTITUTIONS;

APPLICATION PERFORMANCE; HIERARCHICAL MEMORY; MEMORY MANAGEMENT; MEMORY MANAGEMENT TECHNIQUES; MEMORY ORGANIZATIONS; PHYSICAL CONSTRAINTS; SYSTEMATIC EXPLORATION; UNDERLYING PRINCIPLES;

RANDOM ACCESS STORAGE;

EID: 84951003652     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2001.955196     Document Type: Conference Paper

References (22)

1. A. Aggarwal, B. Alpern, A.K. Chandra, and M. Snir. A Model for Hierarchical Memory. In Proc. of the 19th ACM Symposium on Theory of Computing, (1987), 305-314.
2. A. Aggarwal, A.K. Chandra, and M. Snir. Hierarchical Memory with Block Transfer. In Proc. 28th Annual Symposium on Foundations of Computer Science, (1987), 204-216.
3. B. Alpern, L. Carter, E. Feig, and T. Selker. The Uniform Memory Hierarchy Model of Computation. In Algorithmica, vol. 12, (1994), 72-129.
4. N.M. Amato, J. Perdue, A. Pietracaprina, G. Pucci, and M. Mathis. . Predicting performance on SMP's. A case study: The SGI Power Challenge. In Proc. International Parallel and Distributed Processing Symposium, IPDPS 2000, Cancun, MEX, pages 729-737, May 2000.
5. G. Bilardi, K. Ekanadham, and P. Pattnaik. Computational power of pipelined memory hierarchies. 13th ACM Symposium on Parallel Algorithms and Architectures, SPAA 2001, Crete, July 2001.
6. G. Bilardi and F.P. Preparata. Horizons of Parallel Computation. Journal on Parallel and Distributed Computing, Vol. 27, 172-182, 1995.
7. G.Bilardi and F.Preparata Processor-time tradeoffs under bounded-speed message propagation. Part II: lower bounds. Theory of Computing Systems, Vol. 30, 523-546, 1997.
8. G.Bilardi and F.Preparata Processor-time tradeoffs under bounded-speed message propagation. Part II: lower bounds. Theory of Computing Systems, Vol. 32, 531-559, 1999.
9. G. Bilardi and E. Peserico. An Approach toward an Analytical Characterization of Locality and its Portability. IWIA 2000, International Workshop on Innovative Architectures, Maui, Hawai, January 2001.
10. G. Bilardi and E. Peserico. A Characterization of Temporal Locality and its Portability Across Memory Hierarchies. ICALP 2001, International Colloquium on Automata, Languages, and Programming, Crete, July 2001.
11. G. Bilardi, A. Pietracaprina, and P. D'Alberto. On the space and access complexity of computation dags. 26th Workshop on Graph-Theoretic Concepts in Computer Science, Konstanz, Germany, June 2000.
12. S.A. Cook and R.A. Reckhow. Time Bounded Random Access Machines. Journal of Computer System Science, 7:354-375, 1973.
13. J. Fotheringham. Dynamic storage allocation in the ATLAS computer, including an automatic use of a backing store. Communication of the ACM, 4, 10, pp. 435-436, (1961).
14. M. Frigo, C.E. Leiserson, H. Prokop and S. Ramachandran. Cache-Oblivious Algorithms. Proc. 40th Annual Symposium on Foundations of Computer Science, (1999).
15. F. Luccio and L. Pagli. A model of sequential computation with pipelined access to memory. Mathematical Systems Theory, 26(4), 343-356, 1993.
16. R.L. Mattson, J.Gecsei, D.R. Slutz, and I.L. Traiger. Evaluation Techniques for Storage Hierarchies. IBM System Journal, No. 2, 78-117, 1970.
17. V. Milutinovic and M. Valero (Guest Eds.) Special Issue on Cache Memory and Related Problems. IEEE Transactions on Computers, February 1999.
18. S.S. Przybylski. Cache and Memory Hierarchy Design. A Performance Directed Approach. Morgan Kaufmann Publishers, Inc. Palo Alto, CA 1990.
19. J.E. Savage. Models of Computation. Exploring the Power of Computing. Addison-Wesley, Reading, MA, 1998.
20. J.S. Vitter. External Memory Algorithms. Invited paper in Proc. 6th Annual European Symposium on Algorithms, (G.Bilardi et al. Eds.), Springer Verlag, Venice, August 1998, 1-25.
21. M.Wolfe High Performance Compilers for Parallel Computing. Addison-Wesley, 1995.
22. R.C.Whaley and J.J.Dongarra. Automatically Tuned Linear Algebra Software. http://www.netlib.org/atlas/index.html