Early evaluation techniques for low power binding

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 160-165

  Kursun, Eren ^a   Srivastava, Ankur ^a   Memik, Seda Ogrenci ^a   Sarrafzadeh, Majid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Low power design; Metric evaluation; Resource binding; Scheduling

Indexed keywords

COMPUTATIONAL COMPLEXITY; DATA FLOW ANALYSIS; GRAPH THEORY; ITERATIVE METHODS; OPTIMIZATION; PROGRAM COMPILERS; SCHEDULING;

DATA FLOW GRAPHS; POWER DISSIPATION; RESOURCE BINDING;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0036949616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146730     Document Type: Conference Paper

References (16)

1. Chang, J.M., Pedram, M., Register Allocation and Binding for Low Power, Design Automation Conference, (DAC), 1995.
2. Lyuh C.G., Kim T., Liu C.L., An integrated Data Path Optimization for Low Power Based on Network Flow Method, International Conference on Computer Aided Design, (ICCAD), 2001.
3. Ku D., De Micheli G., Relative Scheduling Under Timing Constraints, Design Automation Conference, (DAC), 1990.
4. Kruse L., Schmidt E., Jochens G., Stammermann A., Schulz A., Macii E. and Nebel W., Estimation of Lower and Upper Bounds on the Power Consumption from Scheduled Data Flow Graphs, IEEE Trans. on VLSI Systems, pp. 3-14, Feb- 2001.
5. Dasgupta A., Karri R., Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis, International Symposium on Low Power Electronics and Design, (ISLPED), 1995.
6. Dasgupta A., and Karri R., High-Reliability, Low Energy Microarchitecture Synthesis, IEEE, TCAD, 1998.
7. Hu T.C., Parallel Sequencing and Assembly Line Problems, Operations Research, No. 9, pp. 841-848, 1961.
8. Paulin P., Knight J., Force Directed Scheduling for the Behavioral Synthesis of ASIC's, IEEE Transactions on CAD, Vol. 8, No. 6, pp. 661-679, 1989.
9. Potasman R., Lis J., Nicolau A., Gajski D., Percolation Based Scheduling, Design Automation Conference, (DAC), 1990.
10. Camposano R., Path-based Scheduling for Synthesis, IEEE Transactions on CAD, Vol. 10, No. 1, pp. 85-93, 1990.
11. Ogrenci Memik S., Bozorgzadeh E., Kastner R., Sarrafzadeh M., A Super-Scheduler for Embedded Reconfigurable Systems, International Conference on Computer Aided Design, (ICCAD), 2001.
12. Lee C., Potkonjak M. and Mangione-Smith W.H., MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems International Symposium on Microarchitecture, 1997.
13. SUIF. http://suif.stanford.edu.
14. Raghunathan A., Jha N.K., An Iterative Improvement Algorithm for Low Power Data Path Synthesis, International Conference on Computer Aided Design, (ICCAD), 1995.
15. Gebotys C.H., Low Energy Memory and Register Using Network Flow, Design Automation Conference, (DAC), 1997.
16. Hong S., Kim T., Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method, International Conference on Computer Aided Design (ICCAD), November 2000.