System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2002, Pages 225-230

  Puttaswamy, Kiran ^a   Choi, Kyu Won ^a,b   Park, Jun Cheol ^a   Mooney III, Vincent J ^a   Chatterjee, Abhijit ^a,b   Ellervee, Peeter ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

Design space; Embedded systems; Power performance trade offs; Voltage frequency scaling

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC FREQUENCY CONTROL; PERFORMANCE; REDUCED INSTRUCTION SET COMPUTING; RESPONSE TIME (COMPUTER SYSTEMS); STATIC RANDOM ACCESS STORAGE; VOLTAGE CONTROL;

FREQUENCY SCALING; MEMORY CHIP; OFF-CHIP BUSES; SOFTWARE PACKAGE VCS; STORE BUFFER; VOLTAGE SCALING;

EMBEDDED SYSTEMS;

EID: 0036948874     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581199.581249     Document Type: Conference Paper

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