Real-time video decoding scheme for HDTV set-top boxes

IEEE Transactions on Broadcasting

Volumn 48, Issue 4, 2002, Pages 353-360

  Ling, Nam ^a   Wang, Nien Tsu ^a  

^a Department of Computer Science and Engineering   (United States)

Author keywords

HDTV; MPEG 2; Set top box; Video decoder

Indexed keywords

COMPUTER SIMULATION; DECODING; DIGITAL IMAGE STORAGE; DIGITAL TELEVISION; HIGH DEFINITION TELEVISION; IMAGE COMPRESSION; INTERFACES (COMPUTER); REAL TIME SYSTEMS; TELEVISION BROADCASTING; TELEVISION STANDARDS;

ADVANCED TELEVISION SYSTEMS COMMITTEE; CROSSING DIVIDED METHOD; DIGITAL VIDEO BROADCASTING STANDARD; DUAL DECODING DATAPATH; MOTION PICTURE EXPERTS GROUP; SET TOP BOX; SLICE BAR DECODING METHOD; VIDEO DECODER;

VIDEO SIGNAL PROCESSING;

EID: 0036945687     PISSN: 00189316     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBC.2002.806796     Document Type: Article

References (13)

1. F. Frescura, S. Pielmeier, G. Reali, G. Baruffa, and S. Cacopardi, "DSP based OFDM demodulator and equalizer for professional DVB-T receivers," IEEE Trans. Broadcast., vol. 45, no. 3, pp. 323-332, Sept. 1999.
2. ISO/IEC 13 818-2, "Generic coding of moving pictures and associated audio information," Video, Nov. 1994.
3. A. Cugnini and R. Shen, "MPEG-2 video decoder for the digital HDTV grand alliance system," IEEE Trans. Consumer Electron., vol. 41, no. 3, pp. 748-753, Aug. 1995.
4. C.L. Lee et al., "Implementation of digital HDTV video decoder by multiple multimedia video processors," IEEE Trans. Consumer Electron., vol. 42, no. 3, pp. 395-401. August 1996.
5. O. Duardo et al., "An HDTV video coder IC for ATV receivers," IEEE Trans. Consumer Electron., vol. 43, no. 3, pp. 628-632, Aug. 1997.
6. Z. Yu, S. Yu, M. Chu, and G. Tian, "Design and implementation of HDTV source decoder," IEEE Trans. Consumer Electron., vol. 44, no. 2, pp. 384-387, May 1998.
7. C. L. Lee, "Parallel implementation of motion-compensation for HDTV video decoder," IEEE Trans. Consumer Electron., vol. 44, no. 2, pp. 251-255, May 1998.
8. H. Geib et al., "Reducing memory in MPEG-2 video decoder architecture," IEEE Int. Conf. on Consumer Electron., pp. 176-177, Apr. 1997.
9. J.-H. Li and N. Ling, "Architecture and bus-arbitration schemes for MPEG-2 video decoder," IEEE Trans. Circuits Syst. Video Technol., vol. 9, no. 5, pp. 727-736, Aug. 1999.
10. J.-M. Kim and S.-I. Chae, "A cost-effective architecture for HDTV video decoder in ATSC receivers," IEEE Trans. on Consumer Electronics, vol. 44, no. 4, pp. 1353-1359, November 1998.
11. H. Wang, X. Mao, and L. Yu, "A novel HDTV video decoder and decentralized control scheme," IEEE Trans. Consumer Electron., vol. 47, no. 4, pp. 723-728, Nov. 2001.
12. K. A. Kettler and J. K. Strosnider, "Scheduling analysis of the micro channel architecture for multimedia applications," in Proc. Int. Conf. Multimedia Computing and Systems, 1994, pp. 403-414.
13. D. I. Katcher, H. Arakawa, and J. K. Strosnider, "Engineering and analysis of fixed priority schedulers," IEEE Trans. Software Eng., vol. 19, no. 9, pp. 920-934, Sept. 1993.