Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2001, Pages 226-234

  Oh, Kwang Hoon ^a   Duvvury, Charvaka ^b   Salling, Craig ^b   Banerjee, Kaustav ^a   Dutton, Robert W ^a  

^a Stanford University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE MEASUREMENT; GATES (TRANSISTOR); MOSFET DEVICES; SUBSTRATES;

DEEP SUBMICRON ESD DESIGN; LOW RESISTANCE SUBSTRATE; NON-UNIFORM BIPOLAR CONDUCTION; SINGLE FINGER NMOS TRANSISTOR;

INTEGRATED CIRCUIT TESTING;

EID: 0034995214     PISSN: 00999512     EISSN: None     Source Type: Journal    
DOI: 10.1109/RELPHY.2001.922906     Document Type: Article

References (12)

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3. Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool
4. Non-uniform triggering of gg-nMOST investigated by combined emission microscopy and transmission line pulsing
5. Development of substrate-pumped nMOS protection for a 0.13 μm technology
6. ESD-related process effects in mixed-voltage sub-0.5 μm technologies
7. Analysis of snapback behavior on the ESD capability of sub-0.20 μm NMOS
8. Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes
9. Bipolar transistor modeling of avalanche generation for computer circuit simulation
10. Elimination of non-simultaneous triggering effects in finger-type ESD protection transistor using heterojunction buried layer
11. The effect of silicide on ESD performance
12. Substrate pump NMOS for ESD protection application