Optimization of the maximum delay of global interconnects during layer assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 4, 2001, Pages 503-515

  Saxena, Prashant ^b   Liu, C L ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Deep submicrometer; Dynamic area quotas; Global routing; Interconnect; Layer assignment; Lookahead key; Performance driven routing; Physical design

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; OPTIMIZATION; PERFORMANCE; ROUTERS; TREES (MATHEMATICS);

GLOBAL INTERCONNECTS; LAYER ASSIGNMENT; LOOKAHEAD KEY;

INTERCONNECTION NETWORKS;

EID: 0035306837     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.918209     Document Type: Article

References (30)