Hybrid element method for capacitance extraction in VLSI layout verification system

Proceedings of the International Conference on Software for Electrical Engineering Analysis and Design, ELECTROSOFT

Volumn , Issue , 1996, Pages 125-134

  Nowacka, E B ^a   Meijs, N P vd ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY ELEMENT METHOD; CIRCUIT THEORY; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; VLSI CIRCUITS;

CAPACITANCE EXTRACTION; HYBRID ELEMENT METHOD;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029696665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)