A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1472-1478

  Choi, Mun Kyu ^a   Jeon, Byung Gil ^a   Jang, Nakwon ^a   Min, Byung Jun ^a   Song, Yoon Jong ^a   Lee, Sung Yung ^a   Kim, Hyun Ho ^a   Jung, Dong Jin ^a   Joo, Heung Jin ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CAPACITORS; FERROELECTRIC DEVICES; RANDOM ACCESS STORAGE;

ADDRESS TRANSITION DETECTOR; CURRENT FORCING LATCH SENSE AMPLIFIER; DUAL BIT-LINE REFERENCE VOLTAGE GENERATOR; FERROELECTRIC RANDOM ACCESS MEMORY; GATE-OXIDE CAPACITOR; MAIN BIT-LINE CAPACITANCE; REFERENCE BIT-LINE CAPACITANCE; SINGLE SECTION DATA LINE;

NONVOLATILE STORAGE;

EID: 0036858318     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.802357     Document Type: Article

References (5)

1. Y. B. Chung, et al., "A 3.3 V 4 Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme," IEEE J. Solid-State Circuits, vol. 35, May 2000.
2. J. Yamada, et al., "A 128 kb FeRAM macro for a contact/contactless smart card microcontroller," ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2000.
3. H. B. Kang et al., "A hierarchy bitline boost scheme for sub-1.5 V operation and short precharge time on high density FeRAM," ISSCC Dig. Tech. Papers, pp. 158-159, Feb. 2002.
4. B. G. Jeon et al., "A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme," ISSCC Dig. Tech. Papers, pp. 38-39, Feb. 2001.
5. B. G. Jeon et al., "A 0.4 μm 3.3 V 1T1C 4 Mb nonvolatile ferroelectric with fixed bit-line reference voltage scheme and data protection circuit," ISSCC Dig. Tech. Papers, pp. 272-273, Feb. 2000.