Exploiting data forwarding to reduce the power budget of VLIW embedded processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 252-257

  Sami, M ^a   Sciuto, D ^a   Silvano, C ^a   Zaccaria, V ^a   Zafalom, R ^b  

^a POLITECNICO DI MILANO   (Italy)

^b Advanced System Technology   (Italy)

Author keywords

Forwarding; Low Power; Pipeline Processors; VLIW Embedded Architectures

Indexed keywords

APPLICATION EXAMPLES; EMBEDDED ARCHITECTURE; EXPERIMENTAL EVIDENCE; FORWARDING; LOW POWER; PIPELINE PROCESSOR; POWER OPTIMIZATION; VLIW EMBEDDED PROCESSORS;

BENCHMARKING; DESIGN; EMBEDDED SYSTEMS; EXHIBITIONS; MICROPROCESSOR CHIPS; PIPELINES; VERY LONG INSTRUCTION WORD ARCHITECTURE;

PIPELINE PROCESSING SYSTEMS;

EID: 84893669641     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915034     Document Type: Conference Paper

References (13)

1. J. Hennessy and D. A. Patterson, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann Publishers, San Mateo, CA, Second Edition, 1996.
2. A. Abnous and N. Bagherzadeh, "Pipelining and Bypassing in a VLIW Processor", IEEE Trans. on Parallel and Distributed Systems, Vol. 5, No. 6, June 1994, pp. 658-663.
3. H. Corporaal, "Microprocessor Architectures: from VLIW to TTA", John Wiley and Sons, England, 1997.
4. R. Yung and N. C. Wilhelm, "Caching Processor General Registers", ICCD'95. Proceedings of IEEE International Conference on Computer Design, 1995, pp. 307-312.
5. M. M. Martin, A. Roth, C. N. Fischer, "Exploiting Dead Value Information", MICRO-30, Proceedings of 30th Annual IEEE/ACM International Symposium on Microarchitecture, 1997, pp. 125-135.
6. A. Chandrakasan and R. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits", Proc. of IEEE, 83(4), pp. 498-523, 1995.
7. K. Roy, S. C. Prasad "Low-Power CMOS VLSI Circuit Design", John Wiley and Sons, Inc., Wiley-Interscience, 2000.
8. V. Zyuban and P. Kogge, "The Energy Complexity of Register Files", ISLPED98, Proceedings of International Symposium on Low-Power Electronic Design, Monterey, CA-USA, 1998, pp. 305-310.
9. A. V. Aho, R. Sethi, J. D. Ullman, "Compilers: Principles, Techniques, and Tools", Addison-Wesley, 1986.
10. P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homehood, "Lx: A Technology Platform for Customizable VLIW Embedded Processing", ISCA00, Proceedings of International Symposium on Computer Architecture, Vancouver, BC, Canada, 2000, pp. 203-213.
11. J. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction" IEEE Trans. on Computers, C-30(7):478-490. 1981.
12. W. H. Chen, C. H. Smith and S. C. Fralick "A Fast Computational Algorithm For The Discrete Cosine Transform" IEEE Trans. Commun. vol. COM-25, pp. 1004-1009, Sept 1977.
13. W. H. Press, S. A. Teukolsky, W. T. Vetterling, B. P. Flannery "Numerical Recipes in C: The Art of Scientific Computing " Cambridge Univ Press. Jan 1993.