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Volumn 13, Issue 6, 2002, Pages 529-540

Manufacturing cycle time reduction using balance control in the semiconductor fabrication line

Author keywords

Balance; Bottleneck scheduling; Cycle time reduction; Utilization

Indexed keywords

ALGORITHMS; INDUSTRIAL MANAGEMENT; MATHEMATICAL MODELS; SCHEDULING; THROUGHPUT;

EID: 0036758146     PISSN: 09537287     EISSN: None     Source Type: Journal    
DOI: 10.1080/0953728021000014954     Document Type: Article
Times cited : (26)

References (23)
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  • 9
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    • Lee, Y.H.1    Bhaskaran, K.2    Pinedo, M.3
  • 13
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    • Experimental study on input and bottleneck scheduling for the semiconductor fabrication line
    • Lee, Y.H., Park, J., and Kin, S., 2002, Experimental study on input and bottleneck scheduling for the semiconductor fabrication line. IIE Transactions, 34, 179-190.
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  • 20
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.