High defect coverage with low-power test sequences in a BIST environment

IEEE Design and Test of Computers

Volumn 19, Issue 5, 2002, Pages 44-52

  Girard, Patrick ^a   Landrault, Christian ^a   Pravossoudovitch, Serge ^a   Virazel, Arnaud ^b   Wunderlich, Hans Joachim ^c  

^a LIRMM   (France)

^b UNIVERSITY OF STUTTGART   (Germany)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD IMPACT; RANDOM SINGLE INPUT CHANGE;

BUILT-IN SELF TEST; DIGITAL CIRCUITS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RANDOM PROCESSES; SWITCHING;

CMOS INTEGRATED CIRCUITS;

EID: 0036732545     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2002.1033791     Document Type: Article

References (12)

1. Nanometer technology effects on fault models for IC testing
2. DDQ and delay fault testing
3. Survey of low-power testing of VLSI circuits
4. Bridging and stuck-at faults
5. Model for delay faults based upon paths
6. On hardware generation of random single-input change test sequences
7. Delay fault testing: Choosing between random SIC and random MIC test sequences
8. Built-in logic block observation technique
9. Concurrent built-in logic block observer (CBILBO)
10. Verification testing: A pseudo-exhaustive test technique