On hardware generation of random single input change test sequences

Proceedings of the European Test Workshop

Volumn 2001-January, Issue , 2001, Pages 117-123

  David, R ^a   Girard, P ^b   Landrault, C ^b   Pravossoudovitch, S ^b   Virazel, A ^b  

^a GIPSA LAB   (France)

^b LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRON DEVICE TESTING; HARDWARE; INTEGRATED CIRCUIT TESTING; SOFTWARE TESTING; VLSI CIRCUITS;

DELAY FAULT COVERAGE; DELAY TESTING; FAULT COVERAGES; HIGH-PERFORMANCE CIRCUITS; MULTIPLE INPUTS; QUALITY REQUIREMENTS; SINGLE INPUT CHANGES; SOFTWARE GENERATION;

BUILT-IN SELF TEST;

EID: 0010364613     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2001.946674     Document Type: Conference Paper

References (12)

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