n-pass n-detection fault simulation and its applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 8, 2002, Pages 980-986

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

Fault coverage curve; Fault simulation; n detection fault simulation

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ITERATIVE METHODS; MICROPROCESSOR CHIPS;

FAULT SIMULATION;

ELECTRIC FAULT CURRENTS;

EID: 0036685435     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.800453     Document Type: Article

References (4)

1. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
2. On static test compaction and test pattern ordering for scan designs
3. Defect-oriented test scheduling
4. Fault dictionary compression and equivalence class computation for sequential circuits