Development of a new TDC LSI and a VME module

IEEE Transactions on Nuclear Science

Volumn 49 II, Issue 3, 2002, Pages 1164-1169

  Arai, Yasuo ^a,b   Ikeno, Masahiro ^a   Iri, Sinichi ^c   Sofue, Tatsuya ^c   Sagara, Masahiro ^c   Ohta, Masaya ^c  

^a IEEE   (Japan)

^b INSTITUTE OF PARTICLE AND NUCLEAR STUDIES   (Japan)

^c AMSC Co Ltd   (Japan)

Author keywords

Gate arrays; Large scale integration; Measurement; Time to digital converter

Indexed keywords

GATE ARRAYS; PRECISION MUON TRACKING DETECTOR; TIME TO DIGITAL CONVERTER;

CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; DIGITAL SIGNAL PROCESSING; GATES (TRANSISTOR); LSI CIRCUITS;

RADIATION DETECTORS;

EID: 0036624387     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2002.1039631     Document Type: Article

References (5)

1. Y. Arai and M. Ikeno, "A time digitizer CMOS gate-array with a 250 ps time resolution," IEEE J. Solid-State Circuits, vol. 31, pp. 212-220 Feb. 1996.
2. H. Shirasu, Y. Arai, M. Ikeno, T. Murata, and T. Emura, "A VME 32 ch pipeline TDC module with TMC LSI's," IEEE Trans. Nucl. Sci., vol. 43, pp. 1799-1803, 1996.
3. Y. Arai, "Development of frontend electronics and TDC LSI for the ATLAS MDT," Nucl. Instrum. Methods, vol. A453, pp. 365-371, 2000.
4. Y. AraiZ, Y. Kurumisawa, and T. Emura, "Development and a SEU test of a TDC LSI for the ATLAS muon detector," in Proc. 7th Workshop Electronics for LHC Experiments, Oct. 2001, CERN 2001-005, pp. 185-189, [Online]. Available: http://lhc-electronics-workshop.web.cern.ch/LHC-electronics-workshop/.
5. J. Christiansen and M. Mota, "A high-resolution time interpolator based on a delay locked loop and an RC delay line," IEEE J. Solid-State Circuits, vol. 34, pp. 1360-1366 Oct. 1999.