Test structures for evaluating strong phase shift lithography

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 195-200

  Ashton, Robert A ^a,b   Kane, Brittin C ^a,b   Blatchford, James W ^b,c   Shuttleworth, David M ^b  

^a IEEE   (United States)

^b AGERE SYSTEMS   (United States)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

DUV lithography; Phase shift lithography; Test structures

Indexed keywords

PHASE SHIFT LITHOGRAPHY;

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; ETCHING; GATES (TRANSISTOR); LOGIC GATES; MASKS; PHASE SHIFT; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING; SIZE DETERMINATION; WSI CIRCUITS;

LITHOGRAPHY;

EID: 0036565015     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999592     Document Type: Conference Paper

References (4)

1. Practicing extension of 248 DUV optical lithography using trim-mask PSM
2. Alternating phase shifted mask for logic gate levels, design, and mask manufacturing
3. Bridge and Van der Pauw sheet resistor test structures