Sub-50nm gate patterning using line-trimming with 248 or 193nm litho

Microlithography World

Volumn 11, Issue 2, 2002, Pages

  Pollentier, Ivan ^a   Jaenen, Patrick ^a   Baerts, Christina ^a   Ronse, Kurt ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; GATES (TRANSISTOR); INVESTMENTS; ION IMPLANTATION; MASKS; PHOTORESISTS; POLYSILICON; ULTRAVIOLET RADIATION;

CHAMBER CONDITIONING; GATE PATTERNING; LINE-TRIMMING;

LITHOGRAPHY;

EID: 0036564582     PISSN: 1074407X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (4)

1. Photostabilization: The process of improvement
2. Sub-50nm gate patterning using CD trim and 248nm or 193nm lithography
3. (Sub-) 100nm gate patterning using 248nm alternating PSM
4. Front-end-of-line process development using 193nm lithography