Front-end-of-line process development using 193nm lithography

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4404, Issue , 2001, Pages 56-67

  Pollentier, I ^a   Ercken, M ^a   Eliat, A ^a   Delvaux, C ^a   Jaenen, P ^a   Ronse, K ^a  

^a IMEC   (Belgium)

Author keywords

193nm lithography; Active area; CD control; Front end of line integration; Gate; Implant; LER; Metrology; Process development

Indexed keywords

CMOS INTEGRATED CIRCUITS; DRY ETCHING; FORMAL LOGIC; GATES (TRANSISTOR); SCANNING ELECTRON MICROSCOPY;

CRITICAL DIMENSION (CD) CONTROL;

PHOTOLITHOGRAPHY;

EID: 0034839460     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.425235     Document Type: Conference Paper

References (10)

1. Status of ArF lithography for the 130nm technology node
2. On the maturity of ArF resists: When can they be implemented in manufacturing?
3. Dual damascene back-end patterning using 248nm and 193nm lithography
4. Lithography aspects of dual damascene interconnect technology
5. Mechanism studies of scanning electron microscope measurement effects on 193nm photoresists and the development of improved linewidth measurement methods
6. Study of 193nm resist behavior under SEM inspection: How to reduce line-width shrinkage effect ?
7. Study on 193nm photoresist shrinkage after electron beam exposure
8. Metrology method for the correlation of line edge roughness for different resists before and after etch
9. SION ARC: Material characterization and implication in the lithography process
10. Pattern collapse in high aspect ratio DUV- and 193nm resists