Design of small RSFQ microprocessor based on cell-based top-down design methodology

IEICE Transactions on Electronics

Volumn E85-C, Issue 3, 2002, Pages 659-664

  Matsuzaki, Futabako ^a   Yoda, Kenichi ^a   Koshiyama, Junichi ^a   Motoori, Kei ^a   Yoshikawa, Nobuyuki ^a  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

BDD; Microprocessor; SFQ; Standard cell; Superconducting circuit

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DECISION THEORY; JOSEPHSON JUNCTION DEVICES; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; QUANTUM ELECTRONICS;

BINARY DECISION DIAGRAM; RAPID SINGLE FLUX QUANTUM MICROPROCESSOR; STANDARD CELL; SUPERCONDUCTING CIRCUIT; TOP-DOWN DESIGN METHODOLOGY;

LOGIC DESIGN;

EID: 0036504715     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems
2. A new approach for RSFQ logic circuits based on the binary decision diagram
3. A cell-based design approach for RSFQ circuits using a binary decision diagram
4. A cell-based design approach for RSFQ circuits
5. Top-down RSFQ logic design based on a binary decision diagram
6. Binary decision diagrams
7. Overview of low-power ULSI circuit techniques
8. Transmission of single-flux-quantum pulses along superconducting microstrip lines