Fabrication technology and device performance of sub-50-nm-gate InP-based high electron mobility transistors

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 41, Issue 2 B, 2002, Pages 1094-1098

  Endoh, Akira ^a   Yamashita, Yoshimi ^a   Shinohara, Keisuke ^a,b   Higashiwaki, Masataka ^a,b   Hikosaka, Kohki ^a   Mimura, Takashi ^a   Hiyamizu, Satoshi ^c   Matsui, Toshiaki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY   (Japan)

^c OSAKA UNIVERSITY   (Japan)

Author keywords

Cutoff frequency; Gate length; HEMT; High electron mobility transistor; InAlAs InGaAs; InP; Low temperature process; Short channel effect; Two step recessed gate

Indexed keywords

COMPUTER SIMULATION; CRYSTAL LATTICES; ELECTRON BEAMS; FABRICATION; FIELD EFFECT TRANSISTORS; FREQUENCIES; MONTE CARLO METHODS; SEMICONDUCTING INDIUM COMPOUNDS; TRANSCONDUCTANCE;

SHORT CHANNEL EFFECT;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0036478685     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.41.1094     Document Type: Conference Paper

References (13)