Compact associative-memory architecture with fully parallel search capability for the minimum hamming distance

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 2, 2002, Pages 218-227

  Mattausch, Hans Jürgen ^a,b   Gyohten, Takayuki ^c   Soda, Yoshihiro ^d   Koide, Tetsushi ^a,b  

^a IEEE   (Japan)

^b HIROSHIMA UNIVERSITY   (Japan)

^c MITSUBISHI ELECTRIC CORPORATION   (Japan)

^d SONY CORPORATION   (Japan)

Author keywords

Associative memory; CAM; CMOS; Fully parallel search; Hamming distance; Mixed digital analog circuit; Winner take all circuit; WTA

Indexed keywords

MINIMUM HAMMING DISTANCE;

ANALOG STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; NEURAL NETWORKS; SIGNAL ENCODING; TRANSISTORS;

ASSOCIATIVE STORAGE;

EID: 0036474678     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.982428     Document Type: Article

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