Methodology for predicting solder joint reliability in semiconductor packages

Microelectronics Reliability

Volumn 42, Issue 2, 2002, Pages 301-305

  Pendse, Rajendra D ^a   Zhou, Peng ^b  

^a ChipPAC Inc   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FATIGUE OF MATERIALS; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS; STRAIN; SUBSTRATES;

SEMICONDUCTOR PACKAGES;

ELECTRONICS PACKAGING;

EID: 0036472853     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00130-5     Document Type: Article

References (8)

1. Reliability of controlled collapse interconnections
2. Reliability of plastic ball grid array assembly
3. Testing and measurement techniques applied to electronic packaging development
4. Verification of numerical models used in microelectronic packaging design by interferometric displacement measurement methods
5. Thermo mechanical diagnostics of flip chip BGA structures using phase-shifting electronic speckle pattern interferometry
6. Digital imaging techniques in experimental stress analysis
7. The application of HiTCE ceramic material for LGA-type chip scale package
8. New CBGA package with improved 2nd level reliability