Cycle time estimation for wafer fab with engineering lots

IIE Transactions (Institute of Industrial Engineers)

Volumn 34, Issue 2, 2002, Pages 105-118

  Chung, Shu Hsing ^a   Huang, Hung Wen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ESTIMATION; PROCESS CONTROL; PRODUCTION CONTROL; QUEUEING THEORY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

CYCLE TIME ESTIMATION; ENGINEERING LOTS; MATERIAL FLOW CONTROL;

INDUSTRIAL ENGINEERING;

EID: 0036468403     PISSN: 0740817X     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011935728647     Document Type: Article

References (23)

1. The block-based cycle time estimation algorithm for wafer fabrication factories
2. The use and evaluation of yield model in integrated circuit manufacturing
3. A dynamic forecasting model for job shop flowing prediction and tardiness control
4. Trade-offs in cycle time management: Hot lots
5. Real time control of multiproduct bulk-service semiconductor manufacturing processes
6. Using discrete event simulation to analyze the impact of job priorities on cycle time in semiconductor manufacturing
7. Closed-loop job release control for VLSI circuit manufacturing
8. Dynamic batching heuristics for simultaneous processing
9. A probabilistic cost-based due date assignment model for job shops
10. Due-date based scheduling and control policies in a multiproduct semiconductor wafer fabrication facility
11. How the law of unanticipated consequences can nullify the theory of constraint: The case for balanced capacity in a semiconductor manufacturing line
12. Experience in simulation wafer fabs in the USA and Japan
13. Implementing the results of a simulation in a semiconductor line
14. Modeling the effect of hot lots in semiconductor manufacturing systems
15. Throughput time forecasting model
16. The construction of production planning and scheduling system for an IC foundry in ramp-up
17. Dynamic rules for due-date assignment
18. Scheduling semiconductor wafer fabrication
19. Cost and cycle time performance of fabs based on integrated single-wafer processing