An integrated approach to flow, thermal and mechanical modeling of electronics devices

Thermomechanical Phenomena in Electronic Systems -Proceedings of the Intersociety Conference

Volumn , Issue , 2002, Pages 862-868

  Parry, John ^a   Marooney, Chris ^a   Warner, Matt ^b   Bailey, Chris ^b   Pericleous, Koulis ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b UNIVERSITY OF GREENWICH   (United Kingdom)

Author keywords

CFD; FE; Modeling; Multiphysics; Reliability; Stress; Thermal; Thermomechanical

Indexed keywords

COMPUTATIONAL FLUID DYNAMICS; COMPUTER SIMULATION; ELECTROMAGNETIC COMPATIBILITY; SHEAR STRESS; SOLDERED JOINTS; STRAIN; STRESS ANALYSIS; THERMOMECHANICAL TREATMENT;

ELECTRONICS ASSEMBLY;

ELECTRONICS PACKAGING;

EID: 0036457876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. John Parry, Chris Bailey, Chris Aldham, "Multiphysics Modelling For Electronics Design", ITHERM2000, Las Vegas, p86-93, 2000.
2. M. Warner, J. Parry, C. Bailey, C. Marooney, H. Reeves, K. Pericleous, "FLO/STRESS: An Integrated Stress Solver for the CFD tool FLOTHERM", Proceedings of IPACK 2001, July 8-13, 2001, Kauai, Hawaii, USA.
3. R. Darveaux "Solder Joint Fatigue Life Model", Design and Reliability of Solders and Solder Interconnections, 1997, pp213-218, Pub TMS.
4. "The National Technology Roadmap For Semiconductors", Semiconductor Industry Association, 1997.
5. John Parry, Harvey Rosten and Gary B. Kromann, "The Development of Component-level Thermal Compact Models of a C4/CBGA Interconnect Technology: The Motorola PowerPC 603 and PowerPC 604 RISC Microprocessors", Transactions of IEEE CPMT, Vol. 21, No. 1, Mar. 1998, pp. 104-112.
6. H. Lu, C. Bailey, M. Dusek, C. Hunt and J. Nottay, "Modeling the Fatigue Life of Solder Joints for Surface Mount Resistors", International Symposium on Electronic Materials and Packaging, Hong Kong, p136-143, Pub IEEE, ISBN 0-7803-665479, 2000.
7. Physica, V2.10.http://physica.gre.ac.uk.
8. V. Getkin, A. Bar-Cohen and J Ames, "Coffin-Manson Fatigue Model of Underfilled Flip Chips", IEEE Trans. Comp. Pack. & Man. Tech, Part A, Vol. 20, No. 3, pp. 317-325, 1997.
9. W. Englemaier, "Fatigue Life of Leadless Chip Carriers Using Manson-Coffin Equations", IEEE Trans. Comp. Hybrids, & Man. Tech. Vol. CHMT-6, No. 3, pp. 232-237, Sept. 1983.