Maximum power estimation for CMOS circuits using deterministic and statistical approaches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 134-140

  Wang, Chuan Yu ^b   Roy, Kaushik ^a,b  

^a IEEE

^b PURDUE UNIVERSITY   (United States)

Author keywords

CMOS circuits; Deterministic method; Power estimation; Search; Statistical analysis; Testing

Indexed keywords

ELECTRIC LOSSES; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; MONTE CARLO METHODS;

AUTOMATIC TEST GENERATION (ATG) TECHNIQUE;

CMOS INTEGRATED CIRCUITS;

EID: 0032026460     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661255     Document Type: Article

References (10)

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