Design verification and robust design technique for cross-talk faults

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 449-454

  Paul, Bipul C ^a   Choi, Seung Hoon ^a   Im, Yonghee ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CROSSTALK; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

CROSSTALK FAULTS; DESIGN VERIFICATION; DYNAMIC NOISE MODEL; OPTIMIZED OVERLAYING ARRAY BASED ARCHITECTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035699590     PISSN: 10817735     EISSN: None     Source Type: Journal    
DOI: 10.1109/ATS.2001.990325     Document Type: Article

References (7)

1. Design of portable systems
2. Signal integrity
3. Interconnect tuning strategies for high performance ICs
4. Cad tools for managing signal integrity and congestion simultaneously
5. Dynamic noise analysis in precharge-evaluate circuits
6. On-chip cross talk - The new signal integrity challenge