1.7-W 50-Gbit/s InP HEMT 4:1 multiplexer IC with a multi-phase clock architecture

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 2002, Pages 159-162

  Sano, Kimikazu ^a   Murata, Koichi ^a   Sugitani, Suehiro ^a   Sugahara, Hirohiko ^a   Enoki, Takatomo ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; TIME DIVISION MULTIPLEXING; TIMING CIRCUITS; TRANSCONDUCTANCE;

MULTI-PHASE CLOCK ARCHITECTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036442690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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