Impact of chip-level integration on performance of OLTP workloads

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 3-14

  Barroso, Luiz Andre ^a   Gharachorloo, Kourosh ^a   Nowatzyk, Andreas ^a   Verghese, Ben ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP LEVEL INTEGRATION; MULTIPROCESSOR; ONLINE TRANSACTION PROCESSING WORKLOADS; ORACLE COMMERCIAL DATABASE ENGINE RUNNING; UNIPROCESSOR;

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DATABASE SYSTEMS; INTEGRATED CIRCUIT LAYOUT; ONLINE SEARCHING; ROUTERS;

MICROPROCESSOR CHIPS;

EID: 0033314238     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)