Accelerated SAT-based scheduling of control/data flow graphs

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 395-400

  Memik, Seda Ogrenci ^a   Fallah, Farzan ^b  

^a Engineering IV   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; LINEAR PROGRAMMING; OPTIMIZATION; RESOURCE ALLOCATION;

ACCELERATED BOOLEAN SATISFIABILITY; CONTROL DATA FLOW GRAPH; DATA FLOW GRAPH;

LOGIC DESIGN;

EID: 0036398348     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106801     Document Type: Article

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