Exact closed form formula for partial mutual inductances of on-chip interconnects

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 428-433

  Zhong, Guoan ^a   Koh, Cheng Kok ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EQUIVALENT CIRCUITS; INDUCTANCE; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

GEOMETRY MEAN DISTANCE; ON-CHIP INTERCONNECTS; PARTIAL MUTUAL INDUCTANCES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036398172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. M. Kamon, M. J. Tsuk, and J. K. White. FASTHENRY: A multipole-accelerated 3-D inductance extraction program. IEEE Journal on Microwave Theory and Techniques, 42(9):1750-7158, September 1994.
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8. Ruey-Beei Wu, Chien-Nan Kuo, and Kwei K. Chang. Inductance and resistance computations for three-dimensional multiconductor interconnect structures. IEEE Trans. on Microwave Theory and Techniques, 40(2):263-270, February 1992.