Design considerations in a BiCMOS dual-modulus prescaler

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 177-180

  Dülger, Fikret ^a   Sánchez Sinencio, Edgar ^a   Bellaouar, Abdellatif ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS;

CURRENT CONSUMPTION;

CMOS INTEGRATED CIRCUITS;

EID: 0036313746     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler
2. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
3. A low-power 15-GHz frequency divider in a 0.8-μm silicon bipolar technology
4. A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology