A scalable sorting architecture based on maskable WTA/MAX circuit

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Ou, Shin Hong ^a   Lin, Chi Sheng ^a   Liu, Bin Da ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL SYSTEM ANALYSIS; DECISION MAKING; DIGITAL SIGNAL PROCESSING; IMAGE PROCESSING; VECTORS;

CIRCUIT DESIGN; MAXIMUM CIRCUITS; WINNER TAKE ALL CIRCUIT;

LINEAR INTEGRATED CIRCUITS;

EID: 0036292991     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. A high-precision current-mode WTA-MAX circuit with multichip capability
2. Analysis for a class of winner-take-all model
3. Rail-to-rail multiple-input min/max circuit
4. K-winners-take-all neural net with /spl Theta/(1) time complexity
5. A parallel bit-level maximum/minimum selector for digital and video signal processing
6. How to sort N items using a sorting network of fixed size I/O size
7. Realization of large-scale distributions based on batchers sorters
8. Efficient VLSI architecture for columnsort
9. Data-driven control scheme for linear array: Application to a stable insertion sorter
10. A 512 16-b bit-serial sorter chip
11. Design of k-WTA/sorting network using maskable WTA/MAX circuit