A fast and accurate calibration method for high-speed high-resolution pipeline ADC

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages 800-803

  Li, Xiaopeng ^a   Bugeja, Alex R ^b   Ismail, Mohammed ^c  

^a TEXAS INSTRUMENTS   (United States)

^b Engim Inc   (United States)

^c OHIO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ANALOG TO DIGITAL CONVERSION; CALIBRATION; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; SIGNAL TO NOISE RATIO;

DIGITAL DOMAIN CALIBRATION; ON CHIP MIXED SIGNAL;

FREQUENCY CONVERTERS;

EID: 0036292639     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1011474     Document Type: Article

References (9)

1. Analog-to - Digital converters and their applications in radio receivers
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3. A 13b 40Msample/s CMOS pipelined folding ADC with background offset trimming
4. Digital-domain calibration of multistep analog-to-digital converters
5. A 12b 65Msample/s CMOS ADC with 82dB SFDR at 120MHz
6. A calibrated pipelined ADC architecture using a modified transfer function approach
7. A15-b 5-Msamples/s low-spurious CMOS ADC
8. Multi-Standard CMOS Wireless Receivers-Analysis and Design
9. An architecture and an algorithm for fully digital correction of monolithic pipeline ADCs